半導體元件及其製造方法

專利類型

發明

專利國別 (專利申請國家)

中華民國

專利申請案號

111115375

專利證號

I 808732

專利獲證名稱

半導體元件及其製造方法

專利所屬機關 (申請機關)

國立清華大學

獲證日期

2023/07/11

技術說明

二維層狀半導體僅有數個原子厚度，是未來半導體元件極小化的首選通道材料，然而居高不下的接觸電阻是應用上的瓶頸，本申請案提出的技術就是以標準半導體製程相容的方式大幅降低二維層狀半導體的接觸電阻。本案的技術方法是選擇性地將二維半導體表面第一層的原子移除，在不改變製程環境與位置的條件下直接鍍上接觸電極，產生極佳的金/半接面，降低接觸電阻。其原理是藉由增強接觸金屬與半導體的電子軌域耦合，增加傳輸能帶附近之態密度，大幅增加電子注入之效能。技術特點如下： （1）以氫原子自由基將表面第一層的原子移除，不傷及下層晶體結構 （2）室溫反應 （3）製程條件簡單 （4）反應容易控制 （5）與目前矽製程完全相容 （6）效果顯著（可以降低接觸電阻2個數量級以上） Two-dimensional layered semiconductors are only a few atoms thick, and are the preferred channel materials for the miniaturization of future semiconductor devices. However, the high contact resistance is the bottleneck in application. The technology proposed in this application is compatible with standard semiconductor processes and significantly reduces the contact resistance of 2D layered semiconductors. The technical method of this patent is to selectively remove atoms from the first layer of the two-dimensional semiconductor surface, and directly coat the contact electrodes without changing the process environment and position, resulting in excellent metal/semiconductor junctions and reduced contact resistance. The principle is to increase the density of states near the conduction band by enhancing the coupling of electron orbitals between the contact metal and the semiconductor, thereby greatly increasing the efficiency of electron injection. The technical features are as follows: (1) The atoms in the first layer of the surface are removed by hydrogen atom radicals without damaging the underlying crystal structure (2) Room temperature reaction (3) The process conditions are simple (4) The reaction is easy to control (5) Fully compatible with the current silicon process (6) Remarkable effect (can reduce contact resistance by more than 2 orders of magnitude)

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